The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a hierarchical word line structure (main word lines and sub word lines).
Recently, improved integration and reduced power consumption have been increasingly implemented in the LSIs (Large Scale Integrated Circuits) including those for portable equipments. The data read/write operations with reduced power consumption have been demanded particularly in the semiconductor memory devices such as SRAM (Static Random Access Memory).
FIG. 13 is a block diagram showing the structure of a conventional SRAM. In the SRAM of FIG. 13, a memory cell array MA100 is divided into a plurality of memory blocks BK10, BK11. This SRAM has a hierarchical word line structure including main word lines MWL100, MWL101 and sub word lines SWL100, SWL110, SWL101, SWL111. Sub word drivers SWD100, SWD101 are provided for the memory block BK10, and sub word drivers SWD110, SWD111 are provided for the memory block BK11.
Hereinafter, operation of the SRAM of FIG. 13 will be described.
First, bit line pairs BL100 to BL103, BL110 to BL113 in the respective memory blocks BK10, BK11 are precharged to a prescribed potential.
Then, a column decoder 121 selects a corresponding column in response to a column address signal. A column selection circuit 122 connects a bit line pair BL100 to BL103, BL110 to BL113 corresponding to the column selected by the column decoder 121 to an input/output (I/O) line pair IO. In response to the column address signal, a block selection circuit 123 activates a corresponding block selection signal BS10, BS11. Either the memory block BK10 or BK11 is thus selected.
A row decoder 124 selects a corresponding row in response to a row address signal. A main word line driver 125 activates a main word line MWL100, MLW101 corresponding to the row selected by the row decoder 124.
A sub word driver SWD100, SWD101, SWD110, SWD111 receives at its inputs the active block selection signal BS10, BS11 and a voltage on the activated main word line MWL100, MWL101, and activates a corresponding sub word line SWL100, SWL101, SWL110, SWL111.
The data is then written to/read from a memory cell MC corresponding to both the sub word line SWL100, SWL101, SWL110, SWL111 thus activated by the sub word driver SWD100, SWD101, SWD110, SWD111 and the bit line pair BL100 to BL103, BL110 t o BL113 connected to the I/O line pair IO by the column selection circuit 122.
In the SRAM of FIG. 13, the sub word drivers SWD100, SWD101, SWD110, SWD111 are arranged within the memory cell array MA100, increasing the layout area of the memory cell array MA100.
Moreover, the SRAM of FIG. 13 includes the sub word drivers (SWD100, SWD101), (SWD110, SWD111) for the memory blocks BK10, BK11. when each memory block BK10, BK11 ha s a small number of columns, a small number of memory cells MC are connected to the corresponding sub word drivers SWD100, SWD101, SWD110, SWD111. The rate of the area to be occupied by the memory cells MC in the memory cell array MA100 is therefore reduced.
It is an object of the present invention to provide a semiconductor memory device capable of reducing the layout area of a memory cell array.
It is another object of the present invention to provide a semiconductor memory device capable of increasing the rate of the area to be occupied by the memory cells in the memory cell array.
A semiconductor memory device according to the present invention includes a memory cell array, a block selection circuit, a row decoder, a word driver and a column decoder.
The memory cell array includes a plurality of memory cells, a plurality of main word lines and a plurality of bit line pairs. The plurality of memory cells are arranged in rows and columns. The plurality of main word lines are arranged in the rows, that is, m main word lines are arranged per row (where m is an integer equal to or greater than two). The plurality of bit line pairs are arranged in the columns. The memory cell array is divided into a plurality of memory blocks in the column direction. Each of the plurality of memory blocks further includes a plurality of sub word lines. The plurality of sub word lines are arranged in the rows. Each of the plurality of sub word lines is connected to one of the m main word lines arranged in the corresponding row.
The block selection circuit selects a corresponding one of the plurality of memory blocks in response to a column address signal. The row decoder selects a corresponding row in response to a row address signal. The word driver activates one of the m main word lines, arranged in the row selected by the row decoder, which is connected to the sub word line included in the memory block selected by the block selection circuit. The column decoder selects a corresponding column in response to the column address signal.
In this semiconductor memory device, the row decoder selects a row according to the row address signal. The block selection circuit selects one of the plurality of memory blocks according to the column address signal. The word driver activates one of the m main word lines arranged in the row selected by the row decoder, which is connected to the sub word line included in the memory block selected by the block selection circuit. The sub word line connected to the activated main word line is thus activated. Then, the column decoder selects a column according to the column address signal. The data is thus written to/read from the memory cell specified by the activated sub word line and the column selected by the column decoder.
As described above, this semiconductor memory device includes a plurality of main word lines, i.e., m main word lines per row (where m is an integer equal to or greater than two), a plurality of sub word lines each connected to one of the m main word lines arranged in a corresponding row, and the word driver. This eliminates the need to provide a sub word driver within the memory cell array, allowing for reduction in layout area of the memory cell array. Moreover, since no sub word driver need be provided in each of the plurality of memory blocks, the rate of the area to be occupied by the memory cells in the memory cell array can be increased.
Preferably, the semiconductor memory device further includes n first input/output (I/O) line pairs (where n is a positive integer) and a first column selection circuit. The column decoder selects n columns from the memory block selected by the block selection circuit, in response to the column address signal. The first column selection circuit connects bit line pairs corresponding to the n columns selected by the column decoder to the n first I/O line pairs.
In this semiconductor memory device, data is transmitted between n memory cells and n first I/O line pairs. The n memory cells are specified by both one of the plurality of sub word lines included in the memory block selected by the block selection circuit, i.e., a sub word line connected to the main word line activated by the word driver, and bit line pairs corresponding to the n columns selected by the column decoder.
Preferably, the column decoder further selects p first I/O line pairs from the n first I/O line pairs in response to the column address signal (where p is a positive integer). The semiconductor memory device further includes p second I/O line pairs, and a second column selection circuit. The second column selection circuit connects the p first I/O line pairs selected by the column decoder to the p second I/O line pairs.
In this semiconductor memory device, data is transmitted between p memory cells of the n memory cells and p second I/O line pairs. The n memory cells are specified by both one of the plurality of sub word lines included in the memory block selected by the block selection circuit, i.e., a sub word line connected to the main word line activated by the word driver, and n bit line pairs selected by the column decoder. The p memory cells correspond to the p first I/O line pairs selected by the second column selection circuit.
Preferably, the semiconductor memory device further includes n first I/O line pairs (where n is a positive integer), and p second I/O line pairs (where p is a positive integer), a first column selection circuit, and a second column selection circuit. The column decoder selects n bit line pairs in response to the column address signal. The n bit line pairs include p bit line pairs included in the memory block selected by the block selection circuit. The first column selection circuit connects the n bit line pairs selected by the column decoder to the n first I/O line pairs. The second column selection circuit connects to the p second I/O line pairs p first I/O line pairs of the n first I/O line pairs, which are connected to the p bit line pairs included in the memory block selected by the block selection circuit.
In this semiconductor memory device, data is transmitted between p memory cells and p second I/O line pairs. The p memory cells are specified by both one of the plurality of sub word lines included in the memory block selected by the block selection circuit, i.e., a sub word line connected to the main word line activated by the word driver, and p bit line pairs of the n bit line pairs selected by the column decoder, i.e., p bit line pairs included in the memory block selected by the block selection circuit.
Preferably, each of a plurality of sub word lines included in one of the plurality of memory blocks and each of a plurality of sub word lines included in a memory block adjacent to the memory block are connected to one of the m main word lines arranged in the corresponding row through a common line. This semiconductor memory device allows for a simplified structure.
Preferably, the semiconductor memory device further includes a precharge circuit. The precharge circuit precharges a plurality of bit line pairs included in the memory block selected by the block selection circuit to a prescribed potential.
In this semiconductor memory device, the precharge circuit conducts the precharge operation in the memory block selected by the block selection circuit, allowing for reduction in power consumption.